Table of Contents Previous Chapter

Chapter 3 Floppy Disk Controller

3.1 General Requirements

Table 51 on page 31 is an excerpt from PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture, showing the minimum requirements of the floppy disk controller on CHRP platforms.


Table 51. Summary of Minimum Platform Requirements  
=====================================================================================================================
Subsystem |Specification    |Portable |Personal |Server |Description                                                 
==========|=================|=========|=========|=======|============================================================
Floppy    |                 |O        |O        |O      | Not required, but a means to attach for software installa- 
          |3.5" 1.44 MB MFM |R        |R        |R      |tion must be provided. This may be through a provided       
          |Media sense      |R        |R        |R      |connector or over a network.                                
          |Auto eject       |R        |R        |M      |  Media sense: Implementations must allow polling of the    
          |Manual eject     |R        |R        |R      |drive up to 100x per second to determine the presence of    
          |                 |         |         |       |media in the drive.                                         
          |                 |         |         |       |  A method for manual ejection of floppies is required.     
=====================================================================================================================

Requirements:

3-1. A Floppy Disk Controller that is compliant with the interfaces as defined in this section must be represented in the Open Firmware device tree for the auto-eject version of the device as identified by the following properties; name=fdc, device_type=fdc, and compatible=chrp,fdc. For the non-auto-eject version of the device, it is represented by the following properties; name=fdc, device_type=fdc, and compatible=pnpPNP,700.
3-2. The firmware must configure the Floppy Disk Controller in the PS/2[tm] mode, with enhanced auto-eject or without auto-eject.
3-3. This device must be addressed purely with ISA I/O addresses which can be aliased or non-aliased.
3-4. DMA transfers for the floppy disk controller must be 8-bit DMA slave and must support at least the ISA Compatible Timing mode.
3-5. Interrupts generated by the floppy disk controller must be high true edge sensitive.
Software Implementation Note: The PS/2 mode controllers only support two drives.

Software Implementation Note: The operating system is expected to extract the DMA channel number from the node's dma property. The above requirement means that the operating system need not extract the DMA transfer size, DMA count width, or master vs slave capability from the node's dma property. Firmware must set these fields to the values that match the above requirement. Operating systems are recommended to extract the DMA timing from the node's DMA property, though they are free to default to the ISA Compatibility Timing Mode. Refer to Table 23 on page 18 for information about other timing modes.

Software Implementation Note: The operating system is expected to extract the interrupt number from the node's interrupts property. The above requirement means that the operating system need not extract the interrupt type from the node's interrupts property. Firmware must set this field to the values that match the above requirement.

Hardware Implementation Note: The Floppy interrupts are not tri-stated but left enabled, unlike CHRP requirement 2-1.

3.2 Floppy Disk/Tape Media Supported

Requirements:

3-6. The floppy disk controller must support 3.5 inch media with an unformatted capacity of 2 megabytes and a formatted capacity of 1.44 megabytes.
3-7. The floppy disk controller must support the 3.5 inch media with an unformatted capacity of 4 megabytes and a formatted capacity of 2.88 megabytes for purposes of floppy disk port tape backup units.
It is recommended that the floppy disk controller support 3.5 inch media with an unformatted capacity of 1 megabytes and a formatted capacity of 720 kilobytes to enable the use of legacy media of that density.

3.3 Floppy Disk Controller Open Firmware Properties

Requirements:

3-8. The three sets of registers shown in Table 52 on page 33 must be present in the Open Firmware device tree for the auto-eject version of the device as identified by the following properties; name=fdc, device_type=fdc, and compatible=chrp,fdc.
3-9. The first two sets of registers shown in Table 52 on page 33 must be present in the Open Firmware device tree for the non-auto-eject version of the device as identified by the following properties; name=fdc, device_type=fdc, and compatible=pnpPNP,700.
3-10. This device must be represented as an ISA device and a child of an ISA bridge node in the Open Firmware device tree.
3-11. A floppy disk controller must be reported in the Open Firmware device tree as specified in the CHRP ISA Floppy Device Binding [16].
Table 52 on page 33 gives the registers used by the floppy disk controller.


Table 52. Floppy Disk Controller Registers 
=========================================================================
Offset |Register                             |Open Firmware Reg Property 
=======|=====================================|===========================
0      |Status Register A (SRA)              |(reg[1], size = 6)         
-------|-------------------------------------|                           
1      |Status Register B (SRB)              |                           
-------|-------------------------------------|                           
2      |Digital Output Register (DOR)        |                           
-------|-------------------------------------|                           
3      |Tape Drive Register (TDR)            |                           
-------|-------------------------------------|                           
4      |Main Status Register (MSR)/          |                           
       |Data Rate Select Register (DSR)      |                           
-------|-------------------------------------|                           
5      |Data Register (FIFO)                 |                           
-------|-------------------------------------|---------------------------
0      |Digital Input Register (DIR)/        |(reg[2], size = 1)         
       |Configuration Control Register (CCR) |                           
-------|-------------------------------------|---------------------------
0      |Autoeject Register (AER)             |(reg[3], size = 1)         
       |                                     |                           
=========================================================================

3.4 Diskette Drive Controller Registers

Requirements:

3-12. For the device described herein, all the registers defined in Section 3.4.1, "Status Register A (SRA)," on page 33 through Section 3.4.10, "Autoeject Register (AEJ)," on page 41 must be implemented as described herein.
Two sets of registers are described here, control and status. The control registers each have a unique offset address. Floppy disk operations are split into command, execution and result phases. During the result phase, the status registers described are read through the Data Register FIFO (abbreviated as FIFO).

3.4.1 Status Register A (SRA)

Table 53. Status Register A (SRA) Characteristics 
=============================================================================================
Register  |Register   |Associated   |Offset  |Read/Write      |Value when OF  |Software      
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value   
==========|===========|=============|========|================|===============|==============
1 byte    |Direct     |reg[1]       |0x00    |Read Only       |See Table 54   |See Table 54  
          |           |             |        |                |on page 33     |on page 33    
          |           |             |        |                |               |              
=============================================================================================
Status Register A, SRA, monitors the state of the floppy disk interrupt source and some of the disk interface signals.


Table 54. Status Register A (SRA) 
===============================================================================================================================
Bit | Function                                                                                    |Value when    |Value After  
    |                                                                                             |OF passes to  |Software     
    |                                                                                             |SW            |Reset        
====|=============================================================================================|==============|=============
7   |Interrupt Pending: This active high bit reflects the state of the interrupt source from the  |0             |0            
    |floppy disk controller.                                                                      |              |             
----|---------------------------------------------------------------------------------------------|--------------|-------------
6   |Reserved                                                                                     |x             |x            
----|---------------------------------------------------------------------------------------------|--------------|-------------
5   |Step: Active high bit reflecting the state of the STEP disk interface output.                |0             |0            
----|---------------------------------------------------------------------------------------------|--------------|-------------
4   |-Track 0: Active low bit reflecting the status of the TRK0 disk interface input.             |x             |x            
----|---------------------------------------------------------------------------------------------|--------------|-------------
3   |Head Select: Active high bit reflecting the status of the HDSEL disk interface output.       |0             |0            
----|---------------------------------------------------------------------------------------------|--------------|-------------
2   |-Index: Active low bit reflecting the INDEX disk interface input.                            |x             |x            
----|---------------------------------------------------------------------------------------------|--------------|-------------
1   |-Write Protect: Active low bit reflecting the WP disk interface input.                       |x             |x            
----|---------------------------------------------------------------------------------------------|--------------|-------------
0   |Direction: Active high bit reflecting the DIR disk interface output.                         |0             |0            
    |                                                                                             |              |             
===============================================================================================================================

3.4.2 Status Register B (SRB)

Table 55. Status Register B (SRB) Characteristics 
=============================================================================================
Register  |Register   |Associated   |Offset  |Read/Wrt        |Value when OF  |Software      
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value   
==========|===========|=============|========|================|===============|==============
1 byte    |Direct     |reg[1]       |0x01    |Read Only       |See Table 56   |See Table 56  
          |           |             |        |                |on page 34     |on page 34    
          |           |             |        |                |               |              
=============================================================================================
This read-only register shows the status of signals on the diskette drive interface. The write-data and read-data bits change state for each positive transition of the `-write data' or `-read data' signals.


Table 56. Status Register B 
=====================================================================================================================================
Bit | Function                                                                                          |Value when    |Value After  
    |                                                                                                   |OF passes to  |Software     
    |                                                                                                   |SW            |Reset        
====|===================================================================================================|==============|=============
7,6 |Reserved                                                                                           |x             |x            
----|---------------------------------------------------------------------------------------------------|--------------|-------------
5   |Drive Select 0: Reflects the status of the Drive Select 0 bit in the DOR, Digital Output Register  |x             |x            
    |(address2, bit 0). It is cleared after a hardware reset, not a software reset.                     |              |             
----|---------------------------------------------------------------------------------------------------|--------------|-------------
4   |Write Data: Every inactive edge transition of the WDATA disk interface output causes this bit to   |0             |0            
    |change state.                                                                                      |              |             
----|---------------------------------------------------------------------------------------------------|--------------|-------------
3   |Read Data: Every inactive edge transition of the RDATA disk interface output causes this bit to    |0             |0            
    |change states.                                                                                     |              |             
----|---------------------------------------------------------------------------------------------------|--------------|-------------
2   |Write Gate: Active high bit reflecting the WGATE interface output.                                 |0             |0            
----|---------------------------------------------------------------------------------------------------|--------------|-------------
1   | Motor Enable 1: Active high bit reflecting the status of the MTR1 disk interface output.          |0             |x            
----|---------------------------------------------------------------------------------------------------|--------------|-------------
0   |Motor Enable 0: Active high bit reflecting the status of the MTR0 disk interface output.           |0             |x            
    |                                                                                                   |              |             
=====================================================================================================================================

3.4.3 Digital Output Register (DOR)

Table 57. Digital Output Register (DOR) Characteristics 
=============================================================================================
Register  |Register   |Associated   |Offset  |Read/Wrt        |Value when OF  |Software      
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value   
==========|===========|=============|========|================|===============|==============
1 byte    |Direct     |reg[1]       |0x02    |Read/Write      |See Table 58   |See Table 58  
          |           |             |        |                |on page 35     |on page 35    
          |           |             |        |                |               |              
=============================================================================================
The Digital Output Register, DOR, controls the drive select and motor enable disk interface outputs, enables the DMA logic, and contains a software reset bit.


Table 58. Drive Control Register 
========================================================================================================================================
Bit | Function                                                                                             |Value when    |Value After  
    |                                                                                                      |OF passes to  |Software     
    |                                                                                                      |SW            |Reset        
====|======================================================================================================|==============|=============
7   |Motor Enable 3: This bit controls the MTR3 disk interface output. A 1 in this bit causes the          |0             |x            
    |MTR3 pin to go active.                                                                                |              |             
----|------------------------------------------------------------------------------------------------------|--------------|-------------
6   |Motor Enable 2: This bit controls the MTR2 disk interface output. A 1 in this bit causes the          |0             |x            
    |MTR2 pin to go active.                                                                                |              |             
----|------------------------------------------------------------------------------------------------------|--------------|-------------
5   |Motor Enable 1: This bit controls the MTR1 disk interface output. A 1 in this bit causes the          |0             |x            
    |MTR1 pin to go active.                                                                                |              |             
----|------------------------------------------------------------------------------------------------------|--------------|-------------
4   |Motor Enable 0): This bit controls the MTR0 disk interface output. A 1 in this bit causes the         |0             |x            
    |MTR0 pin to go active.                                                                                |              |             
----|------------------------------------------------------------------------------------------------------|--------------|-------------
3   |Reserved                                                                                              |0             |x            
----|------------------------------------------------------------------------------------------------------|--------------|-------------
2   |-Reset Controller): Writing a 0 to this bit resets the controller. It remains in the reset condition  |0             |x            
    |until a 1 is written to this bit. Software resets do not affect the DSR, CCR and other bits of the    |              |             
    |DOR. This bit must be 0 for at least 100ns before a 1 can be written to it.                           |              |             
----|------------------------------------------------------------------------------------------------------|--------------|-------------
1-0 |Drive Select: These two bits are a binary encoding of the four drive selects DR0-DR3. This in-        |0             |x            
    |sures that only one drive select output can be active at a time.                                      |              |             
========================================================================================================================================
N/A as the value after soft reset means that the bit value is not affected.

3.4.4 Tape Drive Register (TDR)

Table 59. Tape Drive Register (TDR) Characteristics 
=============================================================================================
Register  |Register   |Associated   |Offset  |Read/Wrt        |Value when OF  |Software      
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value   
==========|===========|=============|========|================|===============|==============
1 byte    |Direct     |reg[1]       |0x03    |Read/Write      |See Table 60   |See Table 60  
          |           |             |        |                |on page 36     |on page 36    
          |           |             |        |                |               |              
=============================================================================================
The TDR register is the Tape Drive Register and the floppy disk controller media and drive type register. Only what has been called the "enhanced" mode of operation is supported and documented here.


Table 60. Drive Status Register 
============================================================================================================================================================
Bit | Function                                                                                                                 |Value when    |Value After  
    |                                                                                                                          |OF passes to  |Software     
    |                                                                                                                          |SW            |Reset        
====|==========================================================================================================================|==============|=============
7   |Extra Density: When bit 5 is 0, this media id bit is used with bit 6 as described in Table 61 on page 36 to indi-         |x             |x            
    |cate the type of media currently in the floppy drive                                                                      |              |             
----|--------------------------------------------------------------------------------------------------------------------------|--------------|-------------
6   |High Density: When bit 5 is 0, this media id bit is used with bit 7 as described in Table 61 on page 36 to indi-          |x             |x            
    |cate the type of media currently in the floppy drive.                                                                     |              |             
----|--------------------------------------------------------------------------------------------------------------------------|--------------|-------------
5   |Drive ID 1 Information: The state of this bit is determined by the state of bits 1 and 0 in the Drive ID register.        |x             |x            
    |If this bit is 0, there is valid media ID sense data in bits 7 and 6 of this register. This bit holds the value of bit 1  |              |             
    |of the Drive ID register, when drive 0 is accessed and media sense is configured. It holds the value of bit 3 of          |              |             
    |the Drive ID register, when drive 1 is accessed and media sense is configured. Otherwise, it is set to 1 to indi-         |              |             
    |cate that media information is not available. Valid data should be used only when accessing drives 0 and/or 1.            |              |             
    |Table 61 on page 36 shows what the decoded interpretations of bits 7-5 mean.                                              |              |             
----|--------------------------------------------------------------------------------------------------------------------------|--------------|-------------
4   |Drive ID 0 Information: This bit reflects the value of bit 0 in the Drive ID Register if floppy disk device 0 is          |x             |x            
    |accessed. It reflects the value of bit 2 in the Drive ID Register if floppy disk device 1 is accessed                     |              |             
----|--------------------------------------------------------------------------------------------------------------------------|--------------|-------------
3-2 |Logical Drive Exchange: These bits are reserved, and must be set to zero.                                                 |0             |0            
----|--------------------------------------------------------------------------------------------------------------------------|--------------|-------------
1-0 |Tape Select 1,0: These bits assign a logical drive number to a tape drive. Drive 0 must remain as a boot drive            |0             |0            
    |and cannot be assigned as a tape drive. Table 62 on page 36 shows how these bits assign logical drive numbers             |              |             
    |to tape drives                                                                                                            |              |             
============================================================================================================================================================


Table 61. Media ID Bit Functions 
======================================
Bit 7, 6,5 |Media Type                
===========|==========================
X X 1      |Invalid Data              
-----------|--------------------------
0 0 0      |5.25 in                   
-----------|--------------------------
0 1 0      |2.88 Megabyte (formatted) 
-----------|--------------------------
1 0 0      |1.44 Megabyte (formatted) 
-----------|--------------------------
1 1 0      |720 Kilobyte (formatted)  
           |                          
======================================
Software Implementation Note:The Drive ID register in Table 60 on page 36, is not part of the Floppy Disk Controller register set. It is a register where the chipset involved has stored the Drive IDs for drive 0 and drive 1 on the floppy disk interface. It then makes this information available to the Floppy Disk Controller.


Table 62. Tape Drive Assignment Values 
========================
Bit 1,0 |Drive Selected 
========|===============
00      |None           
--------|---------------
01      |1              
--------|---------------
10      |2              
--------|---------------
11      |3              
        |               
========================

3.4.5 Main Status Register (MSR)

Table 63. Main Status Register (MSR) Characteristics 
===========================================================================================
Register  |Register   |Associated   |Offset  |Read/Write      |Value when OF  |Software    
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value 
==========|===========|=============|========|================|===============|============
1 byte    |Direct     |reg[1]       |0x04    |Read Only       |0x00           |0x00        
          |           |             |        |                |               |            
===========================================================================================
This read-only register facilitates the transfer of data between the system microprocessor and the controller.

Table 64. Diskette Drive Controller Status Register 
===========================================================================================================================================
Bit | Function                                                                                                   |Value when    |Value on  
    |                                                                                                            |OF passes to  |Software  
    |                                                                                                            |SW            |Reset     
====|============================================================================================================|==============|==========
7   |Request for Master: When this bit is 1, the Data register is ready to transfer data with the system micro-  |0             |0         
    |processor                                                                                                   |              |          
----|------------------------------------------------------------------------------------------------------------|--------------|----------
6   |Data Input/Output: This bit indicates the direction of data transfer between the diskette drive controller  |0             |0         
    |and the system microprocessor. When this bit is 1, the transfer is to the system microprocessor; when the   |              |          
    |bit is 0, the transfer is to the controller                                                                 |              |          
----|------------------------------------------------------------------------------------------------------------|--------------|----------
5   |Non-DMA Mode: When this bit is 1, the controller is in the non-DMA mode                                     |0             |0         
----|------------------------------------------------------------------------------------------------------------|--------------|----------
4   |Command in Progress: When this bit is 1, command is being processed.                                        |0             |0         
----|------------------------------------------------------------------------------------------------------------|--------------|----------
3   |Drive 3 Busy: When this bit is 1, diskette drive 3 is in the seek mode.                                     |0             |0         
----|------------------------------------------------------------------------------------------------------------|--------------|----------
2   |Drive 2 Busy: When this bit is 1, diskette drive 2 is in the seek mode                                      |0             |0         
----|------------------------------------------------------------------------------------------------------------|--------------|----------
1   |Drive 1 Busy: When this bit is 1, diskette drive 1 is in the seek mode                                      |0             |0         
----|------------------------------------------------------------------------------------------------------------|--------------|----------
0   |Drive 0 Busy: When this bit is 1, diskette drive 0 is in the seek mode                                      |0             |0         
    |                                                                                                            |              |          
===========================================================================================================================================

3.4.6 Data Rate Select Register (DRS)

Table 65. Data Rate Select Register (DRS) Characteristics 
=============================================================================================
Register  |Register   |Associated   |Offset  |Read/Write      |Value when OF  |Software      
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value   
==========|===========|=============|========|================|===============|==============
1 byte    |Direct     |reg[1]       |0x04    |Write Only      |SeeTable 66    |See Table 66  
          |           |             |        |                |on page 38     |on page 38    
          |           |             |        |                |               |              
=============================================================================================
This write-only register is used to select the data rate and precompensation value for each data rate.


Table 66. Precompensation Select Register 
=====================================================================================================================================
Bit | Function                                                                                          |Value when    |Software     
    |                                                                                                   |OF passes to  |Reset Value  
    |                                                                                                   |SW            |             
====|===================================================================================================|==============|=============
7   |S/W Reset: This bit functions the same as the POR Reset bit, except it is self clearing.           |0             |Not effected 
----|---------------------------------------------------------------------------------------------------|--------------|-------------
6   |Low Power: This bit puts the floppy disk controller into low power mode. What low power            |0             |Not effected 
    |means can vary from manufacturer to manufacturer. The floppy disk controller comes out of low      |              |             
    |power mode after a software reset, or access to the Data Register or Main Status Register.         |              |             
----|---------------------------------------------------------------------------------------------------|--------------|-------------
5   |Reserved: Must be Set to 0.                                                                        |0             |Not effected 
----|---------------------------------------------------------------------------------------------------|--------------|-------------
4-2 |Precompensation Select: These bits select the amount of write precompensation the floppy disk      |0             |Not effected 
    |controller uses when writing bits to the floppy disk drive. Table 67 on page 38 shows the precom-  |              |             
    |pensation values for each bit encoding. Table 69 on page 39 shows the default precompensation      |              |             
    |values for each data rate.                                                                         |              |             
----|---------------------------------------------------------------------------------------------------|--------------|-------------
1-0 |Data Rate Select: These bits set the data rate of the floppy disk controller. Table 69 on page 39  |0             |Not effected 
    |shows how data rates for the floppy disk controller are encoded                                    |              |             
=====================================================================================================================================


Table 67. Precompensation Values 
========================
Bits  |Precompensation  
4 3 2 |Delay            
======|=================
000   |Default          
------|-----------------
001   |41.7 ns          
------|-----------------
010   |83.3 ns          
------|-----------------
011   |125.0 ns         
------|-----------------
100   |166.7 ns         
------|-----------------
101   |208.3 ns         
------|-----------------
110   |250 ns           
------|-----------------
111   |0.0 ns           
      |                 
========================


Table 68. Default Precompensation Values 
===========================
Transfer  |Default         
Rate      |Precompensation 
==========|================
500Kbps   |125ns           
----------|----------------
300Kbps   |125ns           
----------|----------------
250Kbps   |125ns           
----------|----------------
1000Kbps  |41.7ns          
          |                
===========================


Table 69. Data Rate Select Encodings 
=========================
Bits |Data Rate          
     |-------------------
1 0  |MFM      |FM       
=====|=========|=========
00   |500Kbps  |250 Kbps 
-----|---------|---------
01   |300Kbps  |150 Kbps 
-----|---------|---------
10   |250 Kbps |125 Kbps 
-----|---------|---------
11   |1 Mbps   |Illegal  
     |         |         
=========================

3.4.7 Data Register (FIFO)

Table 70. Data Register (FIFO) Characteristics 
===========================================================================================
Register  |Register   |Associated   |Offset  |Read/Wrt        |Value when OF  |Software    
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value 
==========|===========|=============|========|================|===============|============
1 byte    |Direct     |reg[1]       |0x05    |Read/Write      |0x00           |0x00        
          |           |             |        |                |               |            
===========================================================================================
The FIFO (read/write) is used to transfer all commands, data and status between the system and the floppy disk controller. During the command phase, the system writes the command bytes into the FIFO after polling the RQM and DIO bits in the MSR. During the result phase, the system reads the result bytes from the FIFO after polling the RQM and DIO bits in the MSR.

Enabling the FIFO, and setting the FIFO threshold, is done via the Configure command. If the FIFO is enabled, only the execution phase byte transfers use the 16 byte FIFO. The FIFO is always disabled during the command and result phases of a controller operation. If the FIFO is enabled, it is not disabled after a software reset if the LOCK bit is set in the lock command. After a hardware reset, the FIFO is disabled to maintain compatibility with PC-AT systems.

The 16-byte FIFO can be used for DMA, Interrupt, or software polling type transfers during the execution of a read, write, format, or scan command. In addition, the FIFO can be put into a burst or non-burst mode with the mode command. In the burst mode, DRQ or IRQ remains active until all of the bytes have been transferred to or from the FIFO. In the non-burst mode, DRQ or IRQ is deasserted for 350 ns to allow higher priority transfer requests to be serviced. The mode command can also disable the FIFO for either reads or writes separately. The FIFO allows the system a larger latency without causing a disk overrun/underrun error. Typical uses of the FIFO are at the 1 Mbit/s data rate, or with multi-tasking operating systems. The default state of the FIFO is disabled, with a threshold of zero. The default state is entered after a hardware reset.

During the execution phase of a command involving data transfer to/from the FIFO, the software must respond to a data transfer service request based on the following formula:

This formula is good for all data rates with the FIFO enabled or disabled. THRESH is a four bit value programmed in the configure command, which sets the FIFO threshold. If the FIFO is disabled, THRESH is zero in the above formula. The last term of the formula, (16xTICP) is an inherent delay due to the microcode overhead required by the FDC. This delay is also data rate dependent.

The programmable FIFO threshold (THRESH) is useful in adjusting the floppy controller to the speed of the system. In other words, a slow system with a sluggish DMA transfer service request (DRQ for DMA mode or IRQ for interrupt mode). Conversely, a fast system with quick response to a data transfer service request uses a low value of THRESH.

Table 71 on page 40 is a table of TDRP and TICP values.

TDRP - Data Rate Period

TICP - Internal Clock Period

TCP - Clock Period


Table 71. Floppy FIFO Table 
==================================================
MFM Data Rate |TDRP |TICP    |Example TICP Values 
==============|=====|========|====================
1 Mbps        |1000 |3 X TCP |125 ns              
--------------|-----|--------|--------------------
500 Kbps      |2000 |3 X TCP |125 ns              
--------------|-----|--------|--------------------
300 Kbps      |3333 |5 X TCP |208 ns              
--------------|-----|--------|--------------------
250 Kbps      |4000 |6 X TCP |250 ns              
              |     |        |                    
==================================================

3.4.8 Digital Input Register (DIR)

Table 72. Digital Input Register (DIR) Characteristics 
=============================================================================================
Register  |Register   |Associated   |Offset  |Read/Write      |Value when OF  |Software      
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value   
==========|===========|=============|========|================|===============|==============
1 byte    |Direct     |reg[2]       |0x00    |Read Only       |See Table 73   |See Table 73  
          |           |             |        |                |on page 40     |on page 40    
          |           |             |        |                |               |              
=============================================================================================


Table 73. Diskette Drive Controller Status Register 
===================================================================================================================================
Bit | Function                                                                                           |Value when    |Value on  
    |                                                                                                    |OF passes to  |Software  
    |                                                                                                    |SW            |Reset     
====|====================================================================================================|==============|==========
7   |Disk In Place: When this bit is a 1 it reflects that the disk is in place.                          |x             |x         
----|----------------------------------------------------------------------------------------------------|--------------|----------
6-3 |Reserved. Must be set to 0b0000.                                                                    |x             |x         
----|----------------------------------------------------------------------------------------------------|--------------|----------
2,1 |Data Rate Select: These bits indicate the status of the DRATE1-0 bits programmed throught the       |x             |x         
    |DSR or CCR                                                                                          |              |          
----|----------------------------------------------------------------------------------------------------|--------------|----------
0   |(-High Density): This bit is a 0 when the 1 Mb/s or 500 Kbps data rate is chosen, and a 1 when the  |x             |x         
    |300 Kbps or 250 Kbps data rate is chosen.                                                           |              |          
===================================================================================================================================

3.4.9 Configuration Control Register (CCR)

Table 74. Configuration Control Register (CCR) Characteristics 
=============================================================================================
Register  |Register   |Associated   |Offset  |Read/Wrt        |Value when OF  |Software      
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value   
==========|===========|=============|========|================|===============|==============
1 byte    |Direct     |reg[2]       |0x00    |Write Only      |See Table 75   |See Table 75  
          |           |             |        |                |on page 41     |on page 41    
          |           |             |        |                |               |              
=============================================================================================
This write-only register sets the transfer rate.


Table 75. Data Rate Control Register 
=====================================================================================================================
Bit | Function                                                                             |Value when    |Value on  
    |                                                                                      |OF passes to  |Software  
    |                                                                                      |SW            |Reset     
====|======================================================================================|==============|==========
7-2 | Reserved: Must be 0                                                                  |x             |x         
----|--------------------------------------------------------------------------------------|--------------|----------
1   | Data Rate Select: Bits 1-0 select the data rate, as shown in the Table 76 on page 41 |1             |1         
----|--------------------------------------------------------------------------------------|--------------|----------
0   | Data Rate Select: Bits 1-0 select the data rate, as shown in the Table 76 on page 41 |0             |0         
    |                                                                                      |              |          
=====================================================================================================================


Table 76. Data Rate Selection 
=================================
Bits |Data Rate                  
1 0  |                           
=====|===========================
00   |500,000 bits per second    
-----|---------------------------
01   |300,000 bits per second    
-----|---------------------------
10   |250,000 bits per second    
-----|---------------------------
11   |1,000,000 bits per second* 
     |                           
=================================

3.4.10 Autoeject Register (AEJ)

Table 77. Autoeject Register (AEJ) Characteristics 
===========================================================================================
Register  |Register   |Associated   |Offset  |Read/Write      |Value when OF  |Software    
Size      |Addressing |Reg Property |Address |Characteristics |passes to SW   |Reset Value 
==========|===========|=============|========|================|===============|============
1 byte    |Direct     |reg[3]       |0x00    |Read/Write      |0x00           |0x00        
          |           |             |        |                |               |            
===========================================================================================
This table is provided for systems that optionally support floppy disk auto-eject.

The motor must be stopped before doing an eject. To cause an auto-eject, software must write to the least significant bit of this register with a 1, followed by a pause provided by software of at least 10 microseconds, followed by a write of a 0, which will result in the auto-eject. All other bits in this register are reserved, therefore software must use a read-modify-write.

3.5 Floppy Drive Controller Programming Considerations

Each command is initiated by a multibyte transfer from the system microprocessor; the result can be a multibyte transfer back to the system microprocessor. Most transfers consist of three phases:

The Seek, Relative Seek, and Recalibrate commands have no result phase. After issuing these commands, the Sense Interrupt Status command must be issued for proper termination and verification of the head position (Present Cylinder Number parameter or PCN).

3.5.1 Controller Commands

Requirements:

3-13. For the device described herein, the commands described in Section 3.5.1.1, "Configure Command," on page 43 through Section 3.5.1.22, "Write Deleted Data Command," on page 55 must be implemented as specified.
The following are supported commands for diskette drive controller:

3.5.1.1 Configure Command

3.5.1.1.1 Command Phase
Table 78. Configure Command Phase 
===========================================
       |7  |6   |5   |4  |3       |2 |1 |0 
-------|---|----|----|---|--------|--|--|--
Byte 0 |0  |0   |0   |1  |0       |0 |1 |1 
=======|===|====|====|===|========|==|==|==
Byte 1 | 0 |0   |0   |0  |0       |0 |0 |0 
-------|---|----|----|---|--------|--|--|--
Byte 2 |0  |EIS |EFF |PD |Thresh- |  |  |  
       |   |    |    |   |old     |  |  |  
       |   |    |    |   |(THR)   |  |  |  
-------|---|----|----|---|--------|--|--|--
Byte 3 |Precompensation Track Number (PTN)                        
       |                                   
===========================================
3.5.1.1.2 Execution Phase
Internal registers are read.

3.5.1.1.3 Result Phase
This command has no result phase.

3.5.1.2 Dumpreg Command

3.5.1.2.1 Command Phase
Table 79. Dumpreg Command Phase 
=======================================
       |7  | 6 | 5 | 4 | 3 | 2 | 1 | 0 
=======|===|===|===|===|===|===|===|===
Byte 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 
       |   |   |   |   |   |   |   |   
=======================================
3.5.1.2.2 Execution Phase
Internal registers are written.

3.5.1.2.3 Result Phase
Table 80. Dumpreg Result Phase 
=================================================
       |7 |6    |5    |4  |3 |2 |1   |0     
=======|==|=====|=====|===|==|==|====|===========
Byte 0 |Present Track Number - Drive 0                            
-------|-----------------------------------------
Byte 1 |Present Track Number - Drive 1                            
-------|-----------------------------------------
Byte 2 |Present Track Number - Drive 2                            
-------|-----------------------------------------
Byte 3 |Present Track Number - Drive 3                            
-------|-----------------------------------------
Byte 4 |Stepping Rate Time Head Unload Time                        
-------|-----------------------------------------
Byte 5 |Head Load Time               |DMA   
-------|-----------------------------|-----------
Byte 6 |Number of Sectors per Track/End of Track                  
-------|-----------------------------------------
Byte 7 |X |0    |Reserved    |X |GAP |WGATE 
-------|--|-----|------------|--|----|-----------
Byte 8 |O | EIS | EFF |PD | Threshold               
-------|--|-----|-----|---|----------------------
Byte 9 |Precompensation Track Number                              
       |                                    
=================================================

3.5.1.3 Format Track Command

3.5.1.3.1 Command Phase
Table 81. Format Command Phase 
============================================
       |7  | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|=====|===|===|===|====|====|====
Byte 0 | 0 | MFM | 0 | 0 |1  |1   |0   |1   
-------|---|-----|---|---|---|----|----|----
Byte 1 |0  | 0   | 0 | 0 | 0 | HD | US | US 
-------|---|-----|---|---|---|----|----|----
Byte 2 |Number of Data Bytes in Sector                             
-------|------------------------------------
Byte 3 |Sectors per Track                                 
-------|------------------------------------
Byte 4 |Gap Length                                 
-------|------------------------------------
Byte 5 |Fill Byte                                 
       |                                    
============================================
3.5.1.3.2 Execution Phase
The system transfers four ID bytes (track, head, sector, bytes/sector) per sector to the floppy controller via DMA or Non-DMA modes. The entire track is formatted. The data block in the data field of each sector is filled with the data pattern byte.

3.5.1.3.3 Result Phase
Table 82. Format Result Phase  
===========================
Byte 0 |Status Register 0  
-------|-------------------
Byte 1 | Status Register 1 
-------|-------------------
Byte 2 | Status Register 2 
-------|-------------------
Byte 3 | Reserved          
-------|-------------------
Byte 4 | Reserved          
-------|-------------------
Byte 5 | Reserved          
-------|-------------------
Byte 6 | Reserved          
       |                   
===========================

3.5.1.4 Lock Command

3.5.1.4.1 Command Phase
Table 83. Lock Command Phase 
======================================
       |7     | 6 | 5 | 4 |3 |2 |1 |0 
=======|======|===|===|===|==|==|==|==
Byte 0 | Lock | 0 | 0 | 1 |0 |1 |0 |0 
       |      |   |   |   |  |  |  |  
======================================
3.5.1.4.2 Execution Phase
An internal Register is written.

3.5.1.4.3 Result Phase
Table 84. Lock Result Phase 
=====================================
       |7 | 6 | 5 | 4    |3 |2 |1 |0 
=======|==|===|===|======|==|==|==|==
Byte 0 |0 | 0 | 0 | Lock |0 |0 |0 |0 
       |  |   |   |      |  |  |  |  
=====================================

3.5.1.5 Perpendicular Mode Command

3.5.1.5.1 Command Phase
Table 85. Perpendicular Mode Command Phase 
===========================================
       |7  | 6 | 5 | 4 |3  |2  |1   |0     
=======|===|===|===|===|===|===|====|======
Byte 0 |0  |0  |0  |1  |0  |0  |1   |0     
-------|---|---|---|---|---|---|----|------
Byte 1 |OW |0  |D3 |D2 |D1 |D0 |GAP |WGATE 
       |   |   |   |   |   |   |    |      
===========================================
3.5.1.5.2 Execution Phase
Internal registers are written.

3.5.1.5.3 Result Phase
There is no result phase for the Perpendicular Mode command.

3.5.1.6 Read Data Command

3.5.1.6.1 Command Phase
Table 86. Read Data Command Phase 
=============================================
       |7   | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|====|=====|===|===|===|====|====|====
Byte 0 |MT0 | MFM |SK | 0 |0  |1   |1   |0   
-------|----|-----|---|---|---|----|----|----
Byte 1 |0   | 0   | 0 | 0 | 0 | HD | US | US 
-------|----|-----|---|---|---|----|----|----
Byte 2 |Track Number                                 
-------|-------------------------------------
Byte 3 |Head Address                                 
-------|-------------------------------------
Byte 4 |Sector Number                                 
-------|-------------------------------------
Byte 5 |Number of Data Bytes in Sector                             
-------|-------------------------------------
Byte 6 |End-of-Track                                 
-------|-------------------------------------
Byte 7 |Gap Length                                 
-------|-------------------------------------
Byte 8 |Data Length                                 
       |                                     
=============================================
3.5.1.6.2 Execution Phase
Data read from disk drive is transferred to system via DMA or non-DMA modes.

3.5.1.6.3 Result Phase
Table 87. Read Data Result Phase 
=======================================
Byte 0 |Status Register 0
-------|-------------------------------
Byte 1 |Status Register 1
-------|-------------------------------
Byte 2 |Status Register 2
-------|-------------------------------
Byte 3 |Track Number
-------|-------------------------------
Byte 4 |Head Address
-------|-------------------------------
Byte 5 |Sector Number
-------|-------------------------------
Byte 6 |Number of Data Bytes in Sector
       |
=======================================

3.5.1.7 Read Deleted Data Command

3.5.1.7.1 Command Phase
Table 88. Read Deleted Data Command Phase  
============================================
       |7  | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|=====|===|===|===|====|====|====
Byte 0 |MT | MFM |SK |0  |1  |1   |0   |0   
-------|---|-----|---|---|---|----|----|----
Byte 1 |0  | 0   | 0 | 0 | 0 | HD | US | US 
-------|---|-----|---|---|---|----|----|----
Byte 2 |Track Number                                 
-------|------------------------------------
Byte 3 |Head Address                                 
-------|------------------------------------
Byte 4 |Sector Number                                 
-------|------------------------------------
Byte 5 |Number of Data Bytes in Sector                             
-------|------------------------------------
Byte 6 |End-of-Track                                 
-------|------------------------------------
Byte 7 |Gap Length                                 
-------|------------------------------------
Byte 8 |Data Length                                 
       |                                    
============================================
3.5.1.7.2 Execution Phase
Data read from disk drive is transferred to system via DMA or non-DMA modes.

3.5.1.7.3 Result Phase
Table 89. Read Deleted Data Result Phase 
=======================================
Byte 0 |Status Register 0
-------|-------------------------------
Byte 1 |Status Register 1
-------|-------------------------------
Byte 2 |Status Register 2
-------|-------------------------------
Byte 3 |Track Number
-------|-------------------------------
Byte 4 |Head Address
-------|-------------------------------
Byte 5 |Sector Number
-------|-------------------------------
Byte 6 |Number of Data Bytes in Sector
       |
=======================================

3.5.1.8 Read ID Command

3.5.1.8.1 Command Phase
Table 90. Read ID Command Phase  
============================================
       |7  | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|=====|===|===|===|====|====|====
Byte 0 | 0 | MFM | 0 | 0 |1  |0   |1   |0   
-------|---|-----|---|---|---|----|----|----
Byte 1 |0  | 0   | 0 | 0 | 0 | HD | US | US 
       |   |     |   |   |   |    |    |    
============================================
3.5.1.8.2 Execution Phase
The controller reads the first ID field header bytes it can find and reports these bytes to the system in the result bytes.

3.5.1.8.3 Result Phase
Table 91. Read ID Result Phase  
=======================================
Byte 0 |Status Register 0
-------|-------------------------------
Byte 1 |Status Register 1
-------|-------------------------------
Byte 2 |Status Register 2
-------|-------------------------------
Byte 3 |Track Number
-------|-------------------------------
Byte 4 |Head Address
-------|-------------------------------
Byte 5 |Sector Number
-------|-------------------------------
Byte 6 |Number of Data Bytes in Sector
       |
=======================================

3.5.1.9 Read Track Command

3.5.1.9.1 Command Phase
Table 92. Read Track Command Phase  
============================================
       |7  | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|=====|===|===|===|====|====|====
Byte 0 | 0 | MFM | 0 | 0 |0  |0   |1   |0   
-------|---|-----|---|---|---|----|----|----
Byte 1 |0  | 0   | 0 | 0 | 0 | HD | US | US 
-------|---|-----|---|---|---|----|----|----
Byte 2 |Track Number                                 
-------|------------------------------------
Byte 3 |Head Address                                 
-------|------------------------------------
Byte 4 |Sector Number                                  
-------|------------------------------------
Byte 5 |Number of Data Bytes in Sector                             
-------|------------------------------------
Byte 6 |End-of-Track                                 
-------|------------------------------------
Byte 7 |Gap Length                                 
-------|------------------------------------
Byte 8 |Data Length                                 
       |                                    
============================================
3.5.1.9.2 Execution Phase
Data read from the disk drive is transferred to the system via DMA or non-DMA modes.

3.5.1.9.3 Result Phase
Table 93. Read Track Result Phase  
=======================================
Byte 0 |Status Register 0
-------|-------------------------------
Byte 1 |Status Register 1
-------|-------------------------------
Byte 2 |Status Register 2
-------|-------------------------------
Byte 3 |Track Number
-------|-------------------------------
Byte 4 |Head Address
-------|-------------------------------
Byte 5 |Sector Number
-------|-------------------------------
Byte 6 |Number of Data Bytes in Sector
       |
=======================================

3.5.1.10 Recalibrate Command

3.5.1.10.1 Command Phase
Table 94. Recalibrate Command Phase  
=========================================
       |7  | 6 | 5 | 4 | 3 | 2 | 1  | 0  
=======|===|===|===|===|===|===|====|====
Byte 0 | 0 |0  | 0 | 0 |0  |1  |1   |1   
-------|---|---|---|---|---|---|----|----
Byte 1 |0  | 0 | 0 | 0 | 0 |0  | US | US 
       |   |   |   |   |   |   |    |    
=========================================
3.5.1.10.2 Execution Phase
The disk drive head is stepped out to Track 0.

3.5.1.10.3 Result Phase
This command has no result phase.

3.5.1.11 Relative Seek Command

3.5.1.11.1 Command Phase
Table 95. Relative Seek Command Phase  
===========================================
       |7  | 6  | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|====|===|===|===|====|====|====
Byte 0 | 1 |DIR | 0 | 0 |1  |1   |1   |1   
-------|---|----|---|---|---|----|----|----
Byte 1 |0  | 0  | 0 | 0 | 0 | HD | US | US 
-------|---|----|---|---|---|----|----|----
Byte 2 |Relative Cylinder Number                                
       |                                   
===========================================
3.5.1.11.2 Execution Phase
The disk drive head is stepped in or out a programmable number of tracks.

3.5.1.11.3 Result Phase
This command has no result phase.

3.5.1.12 Scan Equal Command

3.5.1.12.1 Command Phase
Table 96. Scan Equal Command Phase  
============================================
       |7  | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|=====|===|===|===|====|====|====
Byte 0 |MT | MFM |SK |1  |0  |0   |0   |1   
-------|---|-----|---|---|---|----|----|----
Byte 1 |0  | 0   | 0 | 0 | 0 | HD | US | US 
-------|---|-----|---|---|---|----|----|----
Byte 2 |Track Number                                 
-------|------------------------------------
Byte 3 |Head Address                                 
-------|------------------------------------
Byte 4 |Sector Number                                 
-------|------------------------------------
Byte 5 |Number of Data Bytes in Sector                             
-------|------------------------------------
Byte 6 |End-of-Track                                 
-------|------------------------------------
Byte 7 |Gap Length                                 
-------|------------------------------------
Byte 8 |Scan Test                                 
       |                                    
============================================
3.5.1.12.2 Execution Phase
Data transferred from the system to the controller is compared to data read from the disk.

3.5.1.12.3 Result Phase
Table 97. Scan Equal Result Phase  
=======================================
Byte 0 |Status Register 0
-------|-------------------------------
Byte 1 |Status Register 1
-------|-------------------------------
Byte 2 |Status Register 2
-------|-------------------------------
Byte 3 |Track Number
-------|-------------------------------
Byte 4 |Head Address
-------|-------------------------------
Byte 5 |Sector Number
-------|-------------------------------
Byte 6 |Number of Data Bytes in Sector
       |
=======================================

3.5.1.13 Scan High or Equal Command

3.5.1.13.1 Command Phase
Table 98. Scan High or Equal Command Phase  
============================================
       |7  | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|=====|===|===|===|====|====|====
Byte 0 |MT | MFM |SK |1  |1  |1   |0   |1   
-------|---|-----|---|---|---|----|----|----
Byte 1 |0  | 0   | 0 | 0 | 0 | HD | US | US 
-------|---|-----|---|---|---|----|----|----
Byte 2 |Track Number                                 
-------|------------------------------------
Byte 3 |Head Address                                 
-------|------------------------------------
Byte 4 |Sector Number                                 
-------|------------------------------------
Byte 5 |Number of Data Bytes in Sector                             
-------|------------------------------------
Byte 6 |End-of-Track                                 
-------|------------------------------------
Byte 7 |Gap Length                                 
-------|------------------------------------
Byte 8 |Scan Test                                 
       |                                    
============================================
3.5.1.13.2 Execution Phase
Data transferred from the systems to the controller is compared to data read from the disk.

3.5.1.13.3 Result Phase
Table 99. Scan High or Equal Result Phase  
=======================================
Byte 0 |Status Register 0
-------|-------------------------------
Byte 1 |Status Register 1
-------|-------------------------------
Byte 2 |Status Register 2
-------|-------------------------------
Byte 3 |Track Number
-------|-------------------------------
Byte 4 |Head Address
-------|-------------------------------
Byte 5 |Sector Number
-------|-------------------------------
Byte 6 |Number of Data Bytes in Sector
       |
=======================================

3.5.1.14 Scan Low or Equal Command

3.5.1.14.1 Command Phase
Table 100. Scan Low or Equal Command Phase  
=============================================
       |7   | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|====|=====|===|===|===|====|====|====
Byte 0 | MT | MFM |SK |1  |1  |0   |0   |1   
-------|----|-----|---|---|---|----|----|----
Byte 1 |0   | 0   | 0 | 0 | 0 | HD | US | US 
-------|----|-----|---|---|---|----|----|----
Byte 2 |Track Number                                 
-------|-------------------------------------
Byte 3 |Head Address                                 
-------|-------------------------------------
Byte 4 |Sector Number                                 
-------|-------------------------------------
Byte 5 |Number of Data Bytes in Sector                             
-------|-------------------------------------
Byte 6 |End-of-Track                                 
-------|-------------------------------------
Byte 7 |Gap Length                                 
-------|-------------------------------------
Byte 8 |Scan Test                                 
       |                                     
=============================================
3.5.1.14.2 Execution Phase
Data transferred from the system to the controller is compared to data read from the disk.

3.5.1.14.3 Result Phase
Table 101. Scan Low or Equal Result Phase  
=======================================
Byte 0 |Status Register 0
-------|-------------------------------
Byte 1 |Status Register 1
-------|-------------------------------
Byte 2 |Status Register 2
-------|-------------------------------
Byte 3 |Track Number
-------|-------------------------------
Byte 4 |Head Address
-------|-------------------------------
Byte 5 |Sector Number
-------|-------------------------------
Byte 6 |Number of Data Bytes in Sector
       |
=======================================

3.5.1.15 Seek Command

3.5.1.15.1 Command Phase
Table 102. Seek Command Phase  
==========================================
       |7  | 6 | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|===|===|===|===|====|====|====
Byte 0 | 0 |0  | 0 | 0 |1  |1   |1   |1   
-------|---|---|---|---|---|----|----|----
Byte 1 |0  | 0 | 0 | 0 | 0 | HD | US | US 
-------|---|---|---|---|---|----|----|----
Byte 2 |New Track Number after Seek                             
       |                                  
==========================================
3.5.1.15.2 .Execution Phase
The disk drive head is stepped in or out to a programmable track.

3.5.1.15.3 Result Phase
This command has no result phase.

3.5.1.16 Sense Drive Status Command

3.5.1.16.1 Command Phase
Table 103. Sense Drive Status Command Phase  
==========================================
       |7  | 6 | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|===|===|===|===|====|====|====
Byte 0 | 0 |0  | 0 | 0 |0  |1   |0   |0   
-------|---|---|---|---|---|----|----|----
Byte 1 |0  | 0 | 0 | 0 | 0 | HD | US | US 
       |   |   |   |   |   |    |    |    
==========================================
3.5.1.16.2 Result Phase
Table 104. Sense Drive Status Result Phase  
===========================
Byte 0 |Status Register 3
       |
===========================

3.5.1.17 Sense Interrupt Status

3.5.1.17.1 Command Phase
Table 105. Sense Interrupt Status Command Phase  
=======================================
       |7  | 6 | 5 | 4 | 3 | 2 | 1 | 0 
=======|===|===|===|===|===|===|===|===
Byte 0 | 0 |0  | 0 | 0 |1  |0  |0  |0  
       |   |   |   |   |   |   |   |   
=======================================
3.5.1.17.2 Execution Phase
The status of the interrupt is reported.

3.5.1.17.3 Result Phase
Table 106. Sense Interrupt Status Result Phase  
=============================
Byte 0 |Status Register 0
-------|---------------------
Byte 1 |Present Track Number
       |
=============================

3.5.1.18 Specify Command

3.5.1.18.1 Command Phase
Table 107. Specify Command Phase  
==============================================
       |7  | 6 | 5 | 4    | 3 | 2 | 1 | 0  
=======|===|===|===|======|===|===|===|=======
Byte 0 | 0 | 0 | 0 | 0    | 0 | 0 | 1 | 1   
-------|---|---|---|------|---|---|---|-------
Byte 1 |Stepping Rate Time| Head Unload Time             
-------|------------------|-------------------
Byte 2 |Head Load Time                |DMA 
       |                              |    
==============================================
3.5.1.18.2 Execution Phase
Internal registers are written.

3.5.1.18.3 Result Phase
This command has no result phase.

3.5.1.19 Verify Command

3.5.1.19.1 Command Phase
Table 108. Verify Command Phase 
============================================
       |7  | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|===|=====|===|===|===|====|====|====
Byte 0 |MT | MFM |SK |1  |0  |1   |1   |0   
-------|---|-----|---|---|---|----|----|----
Byte 1 |EC | 0   | 0 | 0 | 0 | HD | US | US 
-------|---|-----|---|---|---|----|----|----
Byte 2 |Track Number                                 
-------|------------------------------------
Byte 3 |Head Address                                 
-------|------------------------------------
Byte 4 |Sector Address                                 
-------|------------------------------------
Byte 5 |Sector Size                                 
-------|------------------------------------
Byte 6 |End-of-Track                                 
-------|------------------------------------
Byte 7 |Gap Length                                 
-------|------------------------------------
Byte 8 |Byte Transfer Control                                 
       |                                    
============================================
3.5.1.19.2 Execution Phase
Data is read from the disk but not transferred to the system.

3.5.1.19.3 Result Phase
Table 109. Verify Result Phase 
===========================
Byte 0 |Status Register 0
-------|-------------------
Byte 1 |Status Register 1
-------|-------------------
Byte 2 |Status Register 2
-------|-------------------
Byte 3 |Track Number
-------|-------------------
Byte 4 |Head Address
-------|-------------------
Byte 5 |Sector Number
-------|-------------------
Byte 6 |Number of Data Bytes in Sector
       |
===========================

3.5.1.20 Version Command

3.5.1.20.1 Command Phase
Table 110. Version Command Phase  
=======================================
       |7  | 6 | 5 | 4 | 3 | 2 | 1 | 0 
=======|===|===|===|===|===|===|===|===
Byte 0 | 0 |0  | 0 |1  |0  |0  |0  |0  
       |   |   |   |   |   |   |   |   
=======================================
3.5.1.20.2 Result Phase
Table 111. Version Result Phase  
======================================
       |7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 
=======|==|===|===|===|===|===|===|===
Byte 0 |1 |0  |0  |X  |0  |0  |0  |0  
       |  |   |   |   |   |   |   |   
======================================
X can be a 1 or a 0.

3.5.1.21 Write Data Command

3.5.1.21.1 Command Phase
Table 112. Write Data Command Phase  
=============================================
       |7   | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|====|=====|===|===|===|====|====|====
Byte 0 | MT | MFM | 0 | 0 |0  |1   |0   |1   
-------|----|-----|---|---|---|----|----|----
Byte 1 |0   | 0   | 0 | 0 | 0 | HD | US | US 
-------|----|-----|---|---|---|----|----|----
Byte 2 |Track Address                                 
-------|-------------------------------------
Byte 3 |Head Address                                 
-------|-------------------------------------
Byte 4 |Sector Number                                 
-------|-------------------------------------
Byte 5 |Number of Data Bytes in Sector                             
-------|-------------------------------------
Byte 6 |End-of-Track                                 
-------|-------------------------------------
Byte 7 |Gap Length                                 
-------|-------------------------------------
Byte 8 |Data Length                                 
       |                                     
=============================================
3.5.1.21.2 Execution Phase
Data is transferred from the system to the controller via DMA or non-DMA modes and written to the disk.

3.5.1.21.3 Result Phase
Table 113. Write Data Result Phase 
=======================================
Byte 0 |Status Register 0
-------|-------------------------------
Byte 1 |Status Register 1
-------|-------------------------------
Byte 2 |Status Register 2
-------|-------------------------------
Byte 3 |Track Number
-------|-------------------------------
Byte 4 |Head Address
-------|-------------------------------
Byte 5 |Sector Number
-------|-------------------------------
Byte 6 |Number of Data Bytes in Sector
       |
=======================================

3.5.1.22 Write Deleted Data Command

3.5.1.22.1 Command Phase
Table 114. Write Deleted Command Phase  
=============================================
       |7   | 6   | 5 | 4 | 3 | 2  | 1  | 0  
=======|====|=====|===|===|===|====|====|====
Byte 0 | MT | MFM | 0 | 0 |1  |0   |0   |1   
-------|----|-----|---|---|---|----|----|----
Byte 1 |0   | 0   | 0 | 0 | 0 | HD | US | US 
-------|----|-----|---|---|---|----|----|----
Byte 2 |Track Number                                 
-------|-------------------------------------
Byte 3 |Head Address                                 
-------|-------------------------------------
Byte 4 |Sector Number                                 
-------|-------------------------------------
Byte 5 |Number of Data Bytes in Sector                             
-------|-------------------------------------
Byte 6 |End of Track                                 
-------|-------------------------------------
Byte 7 |Gap Length                                 
-------|-------------------------------------
Byte 8 |Data Length                                 
       |                                     
=============================================
3.5.1.22.2 Execution Phase
Data is transferred from the system to the controller via DMA or non-DMA modes and written to the disk.

3.5.1.22.3 Result Phase
Table 115. Write Deleted Result Phase  
=======================================
Byte 0 |Status Register 0
-------|-------------------------------
Byte 1 |Status Register 1
-------|-------------------------------
Byte 2 |Status Register 2
-------|-------------------------------
Byte 3 |Track Number
-------|-------------------------------
Byte 4 |Head Address
-------|-------------------------------
Byte 5 |Sector Number
-------|-------------------------------
Byte 6 |Number of Data Bytes in Sector
       |
=======================================

3.5.1.23 Invalid Command Status

3.5.1.23.1 Result Phase. The following status byte is returned to the system microprocessor when an invalid command has been received.
Table 116. Invalid Command Status Register 
===========================
Byte 0 |Status Register 0
       |
===========================
Bits 6 and 7 in status register 0 are used to indicate command status. When an invalid command is processed, this information is returned to the system microprocessor in the invalid command status byte.

3.5.2 Command Status Registers Provided During Result Phase

This section provides definitions for status registers 0 through 3. These registers are read through the Data Register (FIFO) during the result phase of a floppy disk operation.

Requirements:

3-14. For the device described herein, the Command Status Registers described in Section 3.5.2.1, "Status Register 0 (ST0)," on page 56 through Section 3.5.2.4, "Status Register 3 (ST3)," on page 58 must be implemented as specified.

3.5.2.1 Status Register 0 (ST0)

Table 117. Status Register 0  
=========================================================================================================================================
Bit  | Function                                                                                                |Value when    |Value on  
     |                                                                                                         |OF passes to  |Software  
     |                                                                                                         |SW            |Reset     
=====|=========================================================================================================|==============|==========
7, 6 |Interrupt Code:These bits indicate the command interrupt status as given in Table 118 on page 57.        |0             |0         
-----|---------------------------------------------------------------------------------------------------------|--------------|----------
5    |Seek End: This bit is set to 1 when the diskette drive completes the Seek or Recalibrate command,        |0             |0         
     |or a read or write operation with an implied Seek command.                                               |              |          
-----|---------------------------------------------------------------------------------------------------------|--------------|----------
4    |Equipment Check: This bit is set to 1 if the '-track 0' signal fails to occur after the Recalibrate com- |0             |0         
     |mand is issued or Relative Seek command to step outward beyond track 0                                   |              |          
-----|---------------------------------------------------------------------------------------------------------|--------------|----------
3    |Reserved: This bit is always set to 0                                                                    |0             |0         
-----|---------------------------------------------------------------------------------------------------------|--------------|----------
2    |Head Select: This bit indicates the state of the '-head select' signal after the command was per-        |0             |0         
     |formed. When set to 1, head 1 was selected: when set to 0. head O was selected.                          |              |          
-----|---------------------------------------------------------------------------------------------------------|--------------|----------
1, 0 |Drive Select: These bits indicate the drive that was selected upon command completion                    |0             |0         
     |                                                                                                         |              |          
=========================================================================================================================================


Table 118. Encodings for the Interrupt Code field (bits 7,6 of ST0) 
================================================
Bits 7 6 |Function                              
=========|======================================
0 0      |Normal Termination of Command         
---------|--------------------------------------
0 1      |Abnormal Termination of Command       
---------|--------------------------------------
10       |Invalid Command Issued                
---------|--------------------------------------
11       |Internal drive ready status changed   
         |state during the drive polling mode.  
         |Only occurs after a hardware or soft- 
         |ware reset.                           
         |                                      
================================================

Table 119. Drive Select Bits 
===================
Bits 1 0 |Function 
=========|=========
0 0      |Drive 0  
---------|---------
0 1      |Drive 1  
---------|---------
1 0      |Drive 2  
---------|---------
1 1      |Drive 3  
         |         
===================

3.5.2.2 Status Register 1 (ST1)

Table 120. Status Register 1  
================================================================================================================================
Bit |Function                                                                                                                   
====|===========================================================================================================================
7   |End-of-Track: This bit is set to 1 when the controller tries to gain access to a sector beyond the final sector of a track 
----|---------------------------------------------------------------------------------------------------------------------------
6   |Reserved: This bit is always set to 0.                                                                                     
----|---------------------------------------------------------------------------------------------------------------------------
5   |Cyclic Redundancy Check (CRC) Error: This bit is set to 1 when a CRC error is detected in the ID                           
    |or data field.                                                                                                             
----|---------------------------------------------------------------------------------------------------------------------------
4   |Overrun/Underrun Error: This bit is set to 1 if the system does not service the diskette drive controller within an ad-    
    |equate period of time during data transfers.                                                                               
----|---------------------------------------------------------------------------------------------------------------------------
3   |Reserved: This bit is always set to 0.                                                                                     
----|---------------------------------------------------------------------------------------------------------------------------
2   |No Data: This bit is set to 1 when                                                                                         
    |·  The controller cannot find the sector specified in the ID register during the execution of a Read                       
    |Data, Read Deleted Data, or Read ID or Read Track command.                                                                 
    |·  The controller cannot read the ID field without an error during the execution of a Read ID                              
    |command                                                                                                                    
    |·  The starting sector cannot be found during the execution of a Read Track command                                        
----|---------------------------------------------------------------------------------------------------------------------------
1   |Not Writable: This bit is set to 1 when the '-write-protect' signal is active during a Write Data, Write Deleted Data, or  
    |Format Track command.                                                                                                      
----|---------------------------------------------------------------------------------------------------------------------------
0   |Missing Address Mark: This bit is set to 1 if the controller cannot detect an address mark. When this occurs, bit 0 of     
    |Status Register 2 indicates whether the missing address mark is an ID-address mark or a data-address mark.                 
    |                                                                                                                           
================================================================================================================================

3.5.2.3 Status Register 2 (ST2)

Table 121. Status Register 2 
================================================================================================================================
Bit | Function                                                                                                                  
====|===========================================================================================================================
7   |Reserved: This bit is always set to 0.                                                                                     
----|---------------------------------------------------------------------------------------------------------------------------
6   |Control Mark: This bit is set to 1 when the controller encounters a sector that has a deleted data-address mark during a   
    |Read Data or a Read Deleted Data encounters a data address mark.                                                           
----|---------------------------------------------------------------------------------------------------------------------------
5   |CRC Error in Data Field: This bit is set to 1 if the controller detects an error in the data.                              
----|---------------------------------------------------------------------------------------------------------------------------
4   |Wrong Track: This bit is set to 1 when the track number on the media is different from the track number issued by the      
    |command. When this occurs, bit 2 of Status Register 1 is also set to 1.                                                    
----|---------------------------------------------------------------------------------------------------------------------------
3   |Scan Equal Hit: This bit is set to 1 during the Scan command when the conditions for Equal are satisfied.                  
----|---------------------------------------------------------------------------------------------------------------------------
2   |Scan Not Satisfied: This bit is set to 1 during the Scan Command when the scan conditions are not satisfied.               
----|---------------------------------------------------------------------------------------------------------------------------
1   |Bad Track: This bit is set to 1 when the track number on the media is hex FF and the track number value stored in the      
    |ID      register is not hex FF. When this occurs, bit 2 of Status Register 1 is also set to 1.                             
----|---------------------------------------------------------------------------------------------------------------------------
0   |Missing Address Mark in Data Field: This bit is set to 1 when the controller cannot find a data-address mark. This bit     
    |is set to 0 when an ID-address mark cannot be found. Bit 0 in Status Register 0 is also set if either address mark cannot  
    |be found.                                                                                                                  
    |                                                                                                                           
================================================================================================================================

3.5.2.4 Status Register 3 (ST3)

Table 122. Status Register 3  
=========================================================================================================================================
Bit  |Function                                                                                                                           
=====|===================================================================================================================================
7    |Reserved: This bit is always set to 0                                                                                              
-----|-----------------------------------------------------------------------------------------------------------------------------------
6    |Write Protect: This bit indicates the status of the '-write-protect' signal from the diskette drive. When this bit is set to 1,    
     |the'-write-protect' signal is active.                                                                                              
-----|-----------------------------------------------------------------------------------------------------------------------------------
5    |Reserved: This bit is always set to 1.                                                                                             
-----|-----------------------------------------------------------------------------------------------------------------------------------
4    |Track 0: This bit indicates the status of the '-track O' signal from the diskette drive. When this bit is set to 1, the '-track 0  
     |signal is active.                                                                                                                  
-----|-----------------------------------------------------------------------------------------------------------------------------------
3    |Reserved: This bit is always set to 1.                                                                                             
-----|-----------------------------------------------------------------------------------------------------------------------------------
2    |Head Address: This bit indicates the status of the '-head 1 select' signal from the diskette drive. When this bit is set to 1,     
     |the '-head 1 select' signal is active.                                                                                             
-----|-----------------------------------------------------------------------------------------------------------------------------------
1, 0 |Drive Select: These bits indicate the current selected drive.                                                                      
     |                                                                                                                                   
=========================================================================================================================================

3.6 Media Sense

Requirements:

3-15. The disk drive must be configured in a manner such that the Disk in Place signal, on the drive, is functionally a state indicator of the presence of media. The signal must assert an active level when a disk is present in the drive and an inactive level when there is no disk in the drive.

3.7 Floppy Drive Signal Connector Pin Assignment

Table 123. Signal Connector Pin Assignment 
==================================================
PIN | Signal Description |PIN |Signal Description 
====|====================|====|===================
1   |AUTO EJECT *        |2   |N. C.              
----|--------------------|----|-------------------
3   |Key                 |4   |HD OUT             
----|--------------------|----|-------------------
5   |Ground              |6   |DISK IN PLACE *    
----|--------------------|----|-------------------
7   |Ground              |8   |INDEX              
----|--------------------|----|-------------------
9   |Ground              |10  |DRIVE SELECT 0     
----|--------------------|----|-------------------
11  |Ground              |12  |DRIVE SELECT 1     
----|--------------------|----|-------------------
13  |Ground              |14  |N. C.              
----|--------------------|----|-------------------
15  |Ground              |16  |MOTOR ON           
----|--------------------|----|-------------------
17  |Ground              |18  |DIRECTION          
----|--------------------|----|-------------------
19  |Ground              |20  |STEP               
----|--------------------|----|-------------------
21  |Ground              |22  |WRITE DATA         
----|--------------------|----|-------------------
23  |Ground              |24  |WRITE GATE         
----|--------------------|----|-------------------
25  |Ground              |26  |TRACK 00           
----|--------------------|----|-------------------
27  |Ground              |28  |WRITE PROTECT      
----|--------------------|----|-------------------
29  |Ground              |30  |READ DATA          
----|--------------------|----|-------------------
31  |Ground              |32  |HEAD SELECT        
----|--------------------|----|-------------------
33  |Ground              |34  |DISK CHANGE        
    |                    |    |                   
==================================================
Hardware Implementation Note: Signal pins AUTOEJECT, signal pin 1, DISK IN PLACE, signal pin 6, and HD OUT, signal pin 4, must be gated by Drive Select, if the drive is used in platforms that support multiple drives.

3.8 References

  1. National Semiconductor PC87308VUL SuperI/O Enhanced Sidewinder Lite Plug and Play Compatible Chip, with a Floppy Disk Controller, a Keyboard Controller, a Real-Time Clock, Two UARTs, Full Infrared Support and an IEEE1284 Parallel Port [24].
  2. National Semiconductor PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/O III Premium Green) with Floppy Disk Controller, Dual UARTs, IEEE 1284 Parallel Port, and IDE Interface [26].
Table of Contents Next Chapter PrivacyLegalContact